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Analysis of linear-doped Si/SiC power LDMOSFETs based on device simulation

机译:基于器件仿真的线性掺杂Si / SiC功率LDMOSFET分析

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摘要

This paper presents the design and optimization of a 600 V silicon-on-silicon carbide (Si/SiC) laterally diffused MOSFET with linear doping profile in the drift region for high-temperature applications. The proposed structure has an embedded silicon-on-insulator (SOI) layout through which the traditional graded doping theory for SOI can be applied in the Si/SiC architecture. An SOI counterpart is introduced as a benchmark and modeled alongside the proposed structure. Comparisons between them show that they have the near-identical OFF-state and breakdown characteristics, with a significant tunneling leakage component emerging above 450 V. In the ON state, the Si/SiC device has higher electrical resistance but much lower thermal resistance, leading to less self-heating and higher reliability.
机译:本文介绍了在高温区域中在漂移区内具有线性掺杂分布的600 V碳化硅/碳化硅(Si / SiC)横向扩散MOSFET的设计和优化。所提出的结构具有嵌入式绝缘体上硅(SOI)布局,通过该布局,可以将传统的SOI渐变掺杂理论应用于Si / SiC架构。引入了SOI对应物作为基准,并与建议的结构一起进行了建模。它们之间的比较表明,它们具有几乎相同的截止状态和击穿特性,并且在450 V以上出现了显着的隧穿泄漏分量。在导通状态下,Si / SiC器件具有较高的电阻,但具有较低的热阻,因此以减少自发热和更高的可靠性。

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